MASTAR MOSFET Model

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The MASTAR (Model for Analog Simulation of subThreshold, saturation and weak Avalanche Regions)[1][2] is an analytical model of Metal-Oxide Semiconductor Field-Effect Transistors, developed using the voltage-doping transformation (VDT) technique.[3][4][5][6] MASTAR offers good accuracy and continuity in current and its derivatives in all operation regimes of the MOSFET devices. The model has been successfully used in CAD/EDA simulation tools.[7]

The official ITRS definition of the acronym MASTAR is Model for Assessment of CMOS Technologies And Roadmaps.[8] This software[9][10][11] is developed by STMicroelectronics and is freely distributed on ITRS organization web site.

See also[edit]

References[edit]

  1. ^ Skotnicki, T.; Merckel, G.; Denat, C. (1993). "MASTAR - A Model for Analog Simulation of Subthreshold, Saturation and Weak Avalanche Regions in MOSFETs". [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) (published May 14–15, 1993). pp. 146–147. doi:10.1109/VPAD.1993.724762. ISBN 0-7803-1338-0. S2CID 110860616.
  2. ^ Skotnicki, T.; Denat, C.; Senn, P.; Merckel, G.; Hennion, B. (1994), "A new analog/digital CAD model for sub-halfmicron MOSFETs", Technical Digest., International Electron Devices Meeting (published December 11–14, 1994), pp. 165–168
  3. ^ Skotnicki, T.; Marciniak, W. (1986), "A new approach to threshold voltage modelling of short-channel MOSFETS", Solid-State Electronics, vol. 29, no. 11 (published November 1986), pp. 1115–1127, Bibcode:1986SSEle..29.1115S, doi:10.1016/0038-1101(86)90054-7
  4. ^ Skotnicki, T.; Merckel, G.; Pedron, T. (1988), "The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects", IEEE Electron Device Letters, vol. 9, no. 3 (published March 1988), pp. 109–112, Bibcode:1988IEDL....9..109S, doi:10.1109/55.2058, S2CID 23596110
  5. ^ Skotnicki, T.; Merckel, G.; Pedron, T. (1988), "A new punchthrough current model based on the voltage-doping transformation", IEEE Transactions on Electron Devices, vol. 35, no. 7 (published June 1988), pp. 1076–1086, Bibcode:1988ITED...35.1076S, doi:10.1109/16.3367
  6. ^ Skotnicki, T.; Merckel, G.; Pedron, T. (1989), "Analytical study of punchthrough in buried channel p-MOSFETs", IEEE Transactions on Electron Devices, vol. 36, no. 4 (published April 1989), pp. 690–705, Bibcode:1989ITED...36..690S, doi:10.1109/16.22474
  7. ^ Modeling MOS Devices Using the MASTAR Model with UTMOST III Archived 2008-08-21 at the Wayback Machine
  8. ^ ITRS Models, ITRS, archived from the original on 2013-07-09, retrieved 2013-03-15
  9. ^ Skotnicki, Tomasz; Boeuf, Frédéric (2004), "Optimal scaling methodologies and transistor performance", Published in Book "High Dielectric Constant Materials - VLSI MOSFET Applications" Edited by Howard R. Huff and David Gilmer Springer Series Microelectronics, vol. 16
  10. ^ Skotnicki, Thomas; Hutchby, James A.; King, Tsu-Jae; Wong, H.-S. Philip; Boeuf, Frederic (2005), "The Road To The End Of Cmos Scaling", IEEE Circuits and Devices Magazine, vol. 21, no. 1 (published Jan–Feb 2005), pp. 16–26, doi:10.1109/MCD.2005.1388765, S2CID 6389553
  11. ^ Skotnicki, Thomas; Fenouillet-Beranger, Claire; Gallon, Claire; Bœuf, Frederic; Monfray, Stephane; Payet, Fabrice; Pouydebasque, Arnaud; Szczap, Melanie; Farcy, Alexis; Arnaud, Franck; Clerc, Sylvain; Sellier, Manuel; Cathignol, Augustin; Schoellkopf, Jean-Pierre; Perea, Ernesto; Ferrant, Richard; Mingam, Hervé (2008), "Innovative materials devices and CMOS technologies for low-power mobile multimedia", IEEE Transactions on Electron Devices, vol. 55, no. 1 (published January 2008), pp. 96–130, Bibcode:2008ITED...55...96S, doi:10.1109/TED.2007.911338, S2CID 30700626


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