Lawrence Pileggi

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Lawrence Pileggi
BornMarch 14, 1962
NationalityAmerican
Occupation(s)Professor, Academic, Engineer
AwardsIEEE Fellow, SRC Technical Excellence (1991 and 1999), Aristotle Award, IEEE Van Valkenburg Award, SIA University Researcher Award, Newton Industrial Impact Award
Academic background
EducationB.S. and M.S. in electrical engineering from the University of Pittsburgh, Ph.D. in electrical and computer engineering from Carnegie Mellon University (CMU)
Alma materCarnegie Mellon University
Doctoral advisorRonald A. Rohrer
Academic work
InstitutionsUniversity of Pittsburgh Carnegie Mellon University

Lawrence Pileggi (born Lawrence Pillage, March 14, 1962) is the Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University.[1][2] He is a specialist in the automation of integrated circuits, and developing software tools for the optimization of power grids. Pileggi's research has been cited thousands of times in engineering papers.[3]

Education[edit]

Pileggi received B.S. and M.S. degrees in electrical engineering from the University of Pittsburgh in 1983 and 1984, respectively.[1] He received his Ph.D. in electrical and computer engineering from Carnegie Mellon University (CMU) in 1989.[1][2] His thesis work was the development of the Asymptotic Waveform Evaluation (AWE) algorithm.[4][5] The published paper that described this work received the 1991 IEEE Transactions on CAD Paper Award.[6]

Career[edit]

Pileggi worked as an IC design engineer at Westinghouse Research and Development, Pittsburgh, PA, from 1984 to 1986.[6][7]

After receiving his PhD, Pileggi became an assistant professor of electrical and computer engineering at the University of Texas at Austin in 1989.[6][7] There he and his students developed the open source software tool, RICE, or Rapid Interconnect Circuits Evaluation.[8] RICE was recognized with a 1993 Semiconductor Research Corporation Invention Award.[6][9] Most of his early research at UT Austin focused on RICE and various aspects of timing analysis,[10] including the concept of effective capacitance for delay calculation purposes.[11]

In 1996, Pileggi returned to CMU as an associate professor of electrical and computer engineering.[6] While at CMU, Pileggi and his students developed new methods of model order reduction such as the PRIMA algorithm, based on Krylov subspace methods, which further extends model order reduction of circuits.[12] His paper about PRIMA was awarded the 1999 IEEE Donald O. Pederson Best Paper Award.[13]

Based on predictions that lithography for ICs was fast approaching fundamental limits,[14] Pileggi led the development of design methods for regular fabrics that could accommodate the nanoscale patterning for integrated circuits.[15] The MARCO/DARPA Gigascale Research Center honored him with their inaugural Richard A. Newton Industrial Impact Award in 2007 for his regular fabrics work.[16][17] His regular fabrics research was also the catalyst for launching a startup company, Fabbrix, with five of his former students, which was acquired by PDF Solutions in 2007.[18]

In 2005, Pileggi co-founded Xigmix, a startup that was focused on statistical design methods for analog and mixed-mode circuits.[19] In 2007, Xigmix was acquired by Extreme DA, another startup company founded by Pileggi and former students and colleagues;[19] it focused on the development of new methods for statistical timing analysis of digital circuits and was acquired by Synopsys in 2011.[20]

From 2009 to 2013, Pileggi served as the director of the Center for Circuit and System Solutions (C2S2),[21][22] one of six national centers for advanced research funded by the Semiconductor Research Corporation's (SRC) Focus Center Research Program (FCRP).[23]

Pileggi's more recent research work has been developing a “split circuit” approach to the national electric grid that enables the application of circuit simulation techniques.[24] This work was recognized by a Best Paper Award at the 2017 IEEE Power and Energy Society General Meeting,[25] and it also served as the foundation for the startup company Pearl Street Technologies, which he founded in 2018 with two of his former students.[26][27]

Honors[edit]

Pileggi's development of model order reduction methods resulted in the IEEE Circuits and Systems Society honoring him with the Mac Van Valkenburg Award in 2010.[13][28] In 2012, the ACM/IEEE society awarded with the A. Richard Newton Technical Impact Award in Electronic Design Automation.[29]

  • IEEE Fellow
  • IEEE Transactions on CAD Paper Award, 1991[6]
  • SRC Technical Excellence, 1991 and 1999[30]
  • SRC Invention Award, 1993[6][9]
  • IEEE Donald O. Pederson Best Paper Award, 1999[13]
  • Newton Industrial Impact Award, 2007[30]
  • Aristotle Award, 2008[31]
  • IEEE Van Valkenburg Award, 2010[13][28]
  • National Academy of Inventors Fellow[32]

Selected publications[edit]

Pileggi's research has been cited thousands of times in engineering papers.[3]

  • Pillage, L. T., & Rohrer, R. A. (1990). Asymptotic waveform evaluation for timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4): 352–366.
  • Odabasioglu, A., Celik, M., & Pileggi, L. T. (2003). PRIMA: Passive reduced-order interconnect macromodeling algorithm. In The Best of ICCAD (pp. 433–450). Springer, Boston, MA. ISBN 978-1-4615-0292-0
  • Pillage, L. (1998). Electronic Circuit & System Simulation Methods (SRE). New York: McGraw-Hill, Inc. ISBN 978-0-07-134770-9
  • Qian, J., Pullela, S., & Pillage, L. (1994). Modeling the" effective capacitance" for the rc interconnect of cmos gates. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(12): 1526–1535.
  • Celik, M., Pileggi, L., & Odabasioglu, A. (2002). IC interconnect analysis. Berlin, Germany: Springer Science & Business Media.
  • Pileggi, L., & Schmit, H. (2003). U.S. Patent No. 6,633,182. Washington, DC: U.S. Patent and Trademark Office.
  • Pileggi, L. T., Strojwas, A. J., & Lanza, L. L. (2011). U.S. Patent No. 7,906,254. Washington, DC: U.S. Patent and Trademark Office.
  • Calhoun, B. H., Cao, Y., Li, X., Mai, K., Pileggi, L. T., Rutenbar, R. A., & Shepard, K. L. (2008). Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proceedings of the IEEE, 96(2): 343–365.
  • Zhan, Y., Strojwas, A. J., Li, X., Pileggi, L. T., Newmark, D., & Sharma, M. (2005, June). Correlation-aware statistical timing analysis with non-gaussian delay distributions. In Proceedings of the 42nd annual Design Automation Conference (pp. 77–82). ISBN 978-1-59593-058-3
  • Ratzlaff, C. L., & Pillage, L. T. (1994). RICE: Rapid interconnect circuit evaluation using AWE. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(6), 763–776.

References[edit]

  1. ^ a b c University, Carnegie Mellon. "Larry Pileggi - Electrical and Computer Engineering - College of Engineering - Carnegie Mellon University". www.ece.cmu.edu. Retrieved 2021-01-28.
  2. ^ a b "Lawrence Pileggi". Retrieved 2021-01-27.
  3. ^ a b "Lawrence Pileggi". scholar.google.com. Retrieved 2021-01-28.
  4. ^ Pillage, L.T.; Rohrer, R.A. (April 1990). "Asymptotic waveform evaluation for timing analysis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 9 (4): 352–366. doi:10.1109/43.45867. Retrieved 2021-01-27.
  5. ^ "Asymptotic Waveform Evaluation for Timing Analysis" (PDF). IEEE Transactions on Computer-Aided Design. 9 (4). April 1990.
  6. ^ a b c d e f g "Lawrence Pileggi". ptolemy.berkeley.edu. Retrieved 2021-01-28.
  7. ^ a b "Lawrence T. (Larry) Pileggi". Semiconductor Engineering. Retrieved 2021-01-28.
  8. ^ Ratzlaff, C.L.; Pillage, L.T. (June 1994). "RICE: rapid interconnect circuit evaluation using AWE". IEEE. 13 (6): 763–776. doi:10.1109/43.285250.
  9. ^ a b "Regular Circuit Fabrics for CMOS Design at Nanoscale" (PDF). University of Texas at Austin, the Computer Engineering Research Center. 2005-10-14.
  10. ^ Tesu, I.-C.; Pileggi, L.T. (September 1995). "Timing analysis models for gates and cells with bipolar-transistor output stages". Proceedings of Eighth International Application Specific Integrated Circuits Conference. IEEE. pp. 149–152. doi:10.1109/ASIC.1995.580702. ISBN 0-7803-2707-1. S2CID 61835768.
  11. ^ Qian, J.; Pullela, S.; Pillage, L. (December 1994). "Modeling the "Effective capacitance" for the RC interconnect of CMOS gates". IEEE. 13 (12): 1526–1535. doi:10.1109/43.331409.
  12. ^ Odabasioglu, A.; Celik, M.; Pileggi, L.T. (August 1998). "PRIMA: passive reduced-order interconnect macromodeling algorithm". IEEE. 17 (8): 645–654. doi:10.1109/43.712097. S2CID 5825058.
  13. ^ a b c d "TCAD Best Paper Award". people.ece.umn.edu. Retrieved 2021-01-28.
  14. ^ Palusinski, M; Strojwas, AJ; Maly, W (2001-06-18). "Regularity in physical design". scholar.google.com. Retrieved 2021-01-28.
  15. ^ Pileggi, L.; Schmit, H.; Strojwas, A. J.; Gopalakrishnan, P.; Kheterpal, V.; Koorapaty, A.; Patel, C.; Rovner, V.; Tong, K. Y. (2003-06-02). "Exploring regular fabrics to optimize the performance-cost trade-off". Proceedings of the 40th annual Design Automation Conference. DAC '03. Anaheim, CA, USA: Association for Computing Machinery. pp. 782–787. doi:10.1145/775832.776031. ISBN 978-1-58113-688-3. S2CID 7081770.
  16. ^ "Sept. 15: Carnegie Mellon's Larry Pileggi Wins Aristotle Award for Outstanding Teaching - Carnegie Mellon University | CMU". www.cmu.edu. Retrieved 2021-01-28.
  17. ^ "Center for Silicon System Implementation (CSSI)". research.ece.cmu.edu. Retrieved 2021-01-28.
  18. ^ "Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling | (2016) | Liebmann | Publications | Spie". spie.org. Retrieved 2021-01-28.
  19. ^ a b "Statistical timing pioneer moves to transistors". EE Times. 2007-01-31.
  20. ^ Bailey, Brian (2011-10-07). "Synopsys acquires Extreme DA". EE Times.
  21. ^ "C2S2 Organizational Structure - SRC". www.src.org. Retrieved 2021-01-28.
  22. ^ "ECE Source: May 2019 - Annual Faculty Reinvention". myemail.constantcontact.com. Retrieved 2021-01-28.
  23. ^ "Semiconductor Research Corporation - SRC". www.src.org. Retrieved 2021-01-28.
  24. ^ Pandey, Amritanshu; Jereminov, Marko; Hug, Gabriela; Pileggi, Larry (2017-07-16). "Improving power flow robustness via circuit simulation methods". 2017 IEEE Power & Energy Society General Meeting. IEEE. pp. 1–5. arXiv:1711.01624. doi:10.1109/PESGM.2017.8273753. ISBN 978-1-5386-2212-4. S2CID 7376945.
  25. ^ "Pileggi and students receive Best Paper Award at IEEE PES - Electrical and Computer Engineering - College of Engineering - Carnegie Mellon University". www.ece.cmu.edu. 2017-07-20. Retrieved 2021-01-28.
  26. ^ University, Carnegie Mellon. "Pileggi Named ECE Department Head - News - Carnegie Mellon University". www.cmu.edu. Retrieved 2021-01-28.
  27. ^ "About Pearl Street Technologies". www.pearlstreettechnologies.com. Retrieved 2021-01-28.
  28. ^ a b "IEEE Circuits and Systems Society Mac Van Valkenburg Award | IEEE CAS". ieee-cas.org. Retrieved 2021-01-28.
  29. ^ "A. Richard Newton Technical Impact Award in Electronic Design Automation | IEEE Council on Electronic Design Automation". ieee-ceda.org. Retrieved 2021-01-28.
  30. ^ a b "Lawrence Pileggi IEEE Profile". ieeexplore.ieee.org. Retrieved 2021-01-30.
  31. ^ "2008 Aristotle Award - SRC". www.src.org. Retrieved 2021-01-30.
  32. ^ "National Academy of Inventors".
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